Conventional floating gate flash memory types of EEPROMs (electrically erasable programmable read only memory); utilize a memory cell characterized by a vertical stack of a tunnel oxide (SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate (typically an oxide, nitride, oxide stack), and a control gate over the interlayer dielectric positioned over a crystalline silicon substrate. Within the substrate are a channel region positioned below the vertical stack and source and drain diffusions on opposing sides of the channel region.
The floating gate flash memory cell is programmed by inducing hot electron injection from the channel region to the floating gate to create a non volatile negative charge on the floating gate. Hot electron injection can be achieved by applying a drain to source bias along with a high control gate positive voltage. The gate voltage inverts the channel while the drain to source bias accelerates electrons towards the drain. The accelerated electrons gain 5.0 to 6.0eV of kinetic energy which is more than sufficient to cross the 3.2eV Si—SiO2 energy barrier between the channel region and the tunnel oxide. While the electrons are accelerated towards the drain, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO2 interface under the influence of the control gate electrical field and gain sufficient energy to cross the barrier.
Once programmed, the negative charge on the floating gate increases the threshold voltage of the FET characterized by the source region, drain region, channel region, and control gate. During a “read” of the memory cell, the magnitude of the current flowing between the source and drain at a predetermined control gate voltage indicates whether the flash cell is programmed.
More recently charge trapping dielectric memory cell structures have been developed. A first embodiment, as represented by the cross section diagram of FIG. 1a, includes a bit line oxide structure. The cells 10a and 10b are fabricated on a semiconductor substrate 12. Each cell 10 is characterized by a vertical stack of an insulating tunnel layer 14, a charge trapping dielectric layer 20a, 20b, and a top dielectric layer 22a, 22b formed over channel regions 24a, 24b of the substrate 12. Such stack may be referred to as an ONO stack because the insulating tunnel layer 14 and the top dielectric layer 22 are typically an oxide while the center charge trapping dielectric layer is typically a nitride compound. The channel regions 24 are separated from each other, and defined by, bitline implants 18a, 18b, and 18c within the substrate 12. The ONO stacks are separated from each other, and defined by bit line oxide regions 16a, 16b, and 16c which are areas of the tunnel dielectric layer 14 above the bit line implants 18 that are thicker than the areas of the tunnel dielectric layer 14 that are over the channel regions 24.
Above the ONO stacks are a plurality of spaced apart polysilicon word lines 26 that are perpendicular to the bit line implants 18. Each word line is positioned above the top dielectric layer 22b of all calls within a row and each word line is perpendicular to the bit lines.
Similar to the floating gate device, the charge trapping dielectric memory cell 10 is programmed by inducing hot electron injection from the channel region 24 to the nitride layer 20 to create a non volatile negative charge within charge traps existing in the nitride layer 20. Again, hot electron injection can be achieved by applying a drain-to-source bias (e.g. bit line 18b to bit line 18a bias for programming cell 10a) along with a high positive voltage on the polysilicon word line 26 which forms a control gate over the cell 10a. The high voltage on the word line 26 inverts the channel region 24a while the drain-to-source bias accelerates electrons towards the drain bitline 18b. The accelerated electrons gain 5.0 to 6.0 eV of kinetic energy which is more than sufficient to cross the 3.2 eV Si—SiO2 energy barrier between the channel region 24 and the tunnel oxide layer 14. While the electrons are accelerated towards the drain bitline 18b, those electrons which collide with the crystalline lattice are re-directed towards the Si—SiO2 interface under the influence of the control gate electrical field and have sufficient energy to cross the barrier.
Because the charge trapping layer 20 stores the injected electrons within traps and is otherwise a dielectric, the trapped electrons remain localized within a charge storage region that is dose to the drain region bit line to which the positive voltage was applied. As such, the charge trapping dielectric memory device can be used to store two bits of data, one near each of the bit lines of each cell.
The array is typically fabricated by first applying the ONO layer to the top surface of the substrate, etching back the ONO layer to the top surface of the substrate in the bit line regions, implanting the bit line regions, oxidizing the bit line regions to form the bit line oxides, and then applying the word lines to the top of the remaining ONO layer and the bit line oxides.
A second embodiment of a charge trapping dielectric memory cell structure is a planar structure as represented by the diagram of FIG. 1b. Cells 30a and 30b are fabricated on a semiconductor substrate 32. Positioned over the semiconductor substrate 32 is a vertical stack of an insulating tunnel layer 34, a charge trapping dielectric layer 38, and a top dielectric layer 40 positioned over the substrate 32.
Within the substrate are a plurality of parallel, and spaced apart, bit line implants 36a, 36b, and 36c which define a plurality of channel regions 44a, 44b, each of which is between adjacent bit line implants. Above the top dielectric layer 40 are a plurality of parallel, spaced apart, polysilicon word lines which are perpendicular to the bit line implants 36 and the channel regions 44. Each dielectric memory cell is defined by an intersection of a word line 42 and a channel region 44.
A challenge with existing memory cell array structures is that the dimensions are large. First, it should be appreciated that each bit line has a high resistance. It has been empirically determined that using present fabrication technologies that a bit line may have on the order of 100 Ohms of resistance per bit line. As such, accurate control of bit line voltage at a particular cell requires that bit lines be quite wide and that multiple contacts be placed within the array such that each cell is relatively close to a contact. The wide bit lines and the quantity of contacts within the core region of a memory array increases the overall dimension of an array of cells.
Secondly, the architecture wherein bit lines are implanted within the substrate and run perpendicular to word lines combined with the wide bit line requirement further increases the overall dimension of an array of cells.
Consequently, In accordance with a generalized industry need to reduce the size of memory cell arrays, a specific need exists for a memory cell architecture, and a fabrication process therefore, that provides for a more compact arrangement of memory cells within the array without suffering the disadvantages stated above.